Below are CVC simulation times for various Verilog designs you can download and run. Designs and simulation times are provided to illustrate CVC's unmatched price/performance.

If you simply want to see CVC's performance compared to other simulators on one design, please visit the Verilator benchmarks page.

You can obtain an evaluation copy of CVC so that you can run these designs and see CVC's performance for yourself. To run the benchmarks on CVC or any other Verilog simulator, simple click on 'source' to download the Verilog source and pass in the Verilog file list (usually with -f run.flist) to the simulator. For example to run the usb11 open core design with CVC:

%tar xvjf usb11.tar.bz2
%cd usb11
%cvc +verbose -f run.flist
%cvcsim

All example design source directories have a 'run.flist' standard Verilog -f option argument that contains the list of files needed to run the simulation. A 'cvc.log' file is also present in the top level of the directory. It contains expected simulation results and times. For CVC, you need to use the +verbose option so that compilation, simulation and loading times are printed.

All simulations can be preformed from the top level directory by simply passing in the 'run.flist' Verilog file list.

Designs are from www.opencores.com with minor modifications so that they are easy to run on any simulator. Listed CVC simulation times were run on an Intel 3GHZ E8400 processor with DDR2 800 memory.